1. Field of the Invention
This invention pertains to semiconductor packaging, and more particularly, to a method of fabricating a very thin chip size semiconductor package (xe2x80x9cVCSPxe2x80x9d).
2. Description of the Related Art
An integrated circuit(xe2x80x9cICxe2x80x9d) is formed on a single die, or xe2x80x9cchip,xe2x80x9d that is cut from a semiconductor wafer containing a large number of identical dies. IC dies are relatively small and fragile, and are susceptible to harmful environmental elements, particularly moisture. Accordingly, for their effective use, they must be packaged in robust, yet affordable packages capable of protecting them from the environment and enabling them to be reliably mounted to, for example, a printed circuit board (xe2x80x9cPCBxe2x80x9d) and interconnected with associated electronic components mounted thereon.
The recent trend toward miniaturized electronic devices, including cellular phones, laptop computers and their many peripherals, global positioning satellite (xe2x80x9cGPSxe2x80x9d) receivers, and the like, has provided a strong incentive to the semiconductor packaging industry to develop correspondingly smaller IC packages that have enhanced functionality.
One response to this trend has been the recent development of so-called ball grid array (xe2x80x9cBGAxe2x80x9d), land grid array (xe2x80x9cLGAxe2x80x9d), and lead-less chip carrier (xe2x80x9cLCCxe2x80x9d) packages that lack conventional leads, have a xe2x80x9cfootprintxe2x80x9d the same size as the package, and are xe2x80x9cchip sized,xe2x80x9d i.e., have virtually the same length and width as those of the IC chip contained therein. While these types of packages do afford a satisfactory response to the need for IC packages having smaller footprints and greater functionality, there is still room for their improvement, particularly in regard to their thickness, which has not seen a reduction corresponding to the reduction in size of their footprints.
The present invention effectively addresses the challenge of substantially reducing the thickness of IC packages by disclosing a method of manufacturing a BGA-, LGA- or LCC-type of very thin, chip size semiconductor package (xe2x80x9cVCSPxe2x80x9d).
The method of present invention enables fabrication of a xe2x80x9cVCSPxe2x80x9d having a length and width that are nearly the same as those of the semiconductor chip contained therein, and in one embodiment, a thickness of less than 40 mils (1 mil={fraction (1/1000)} in.), i.e., less than 0.5 mm. In another embodiment, the VCSP""s can be stacked one on top of the other to provide enhanced mounting density. The method is amenable to the simultaneous production of a large number of VSCP""s in the form of an array.
The method comprises providing a semiconductor wafer having a first, front or xe2x80x9cactive,xe2x80x9d side with a plurality of finished IC chips formed integrally therein, an opposite second, xe2x80x9cbackxe2x80x9d side, and a given thickness between the first and second sides. The thickness of the wafer is then substantially reduced from the back side of the wafer, which in one embodiment, comprises grinding the back side of the wafer down to remove a substantial portion of its thickness.
When the thickness of the wafer has been reduced by the desired amount, the individual IC chips are singulated from the wafer to provide a plurality of IC chips whose thickness is substantially reduced compared to that of conventional singulated IC chips.
An array of integral insulative substrates is provided, each substrate having a first surface with a plurality of metal pads thereon. The thinned-down chips are electrically connected to corresponding ones of the substrates in the array using the flip chip connection method.
The spaces between the chips and the substrates are underfilled with a liquid epoxy to seal the flip chip connection and the active surface of the chip against moisture. The individual substrates are then singulated close to the periphery of their associated chips to separate the individual VSCPs from the array. In an alternative embodiment, a margin of the top surface of the substrates around the periphery of the chips is left free of epoxy and is provided with a plurality of lands to which a second VSCP can be connected to the first in stacked fashion.